GPUThor generates between 72,000 and 377,000 bit flips per gigabyte on the tested NVIDIA GPUs with no ECC protections, a rate the University of Toronto researchers who published the work say makes practical root-level attacks far more achievable than prior GPU Rowhammer concepts.
How GPUThor changes the Rowhammer playbook
Rowhammer attacks induce bit flips by repeatedly accessing — “hammering” — memory rows so that neighboring bits change state. The University of Toronto paper describes a set of adjustments that let GPUThor avoid existing GDDR6 mitigations and dramatically increase effective hammering. The researchers tailored hammering to follow a non-uniform access pattern and accounted for two undocumented GPU behaviors: how repeated memory requests are coalesced and how frequently Target Row Refresh (TRR) activates. Those changes produced 6.6 times more aggressor-row activations than earlier GPU attacks from the same group and generated between 72,000 and 377,000 flips per GB on the tested GPUs when ECC protections were not present.
Confirmed impact on Ampere-class workstation GPUs
The attack was demonstrated against Ampere-class NVIDIA workstation GPUs with GDDR6 memory, specifically the RTX A4000, RTX A4500, RTX A5000, and RTX A6000 — models the paper notes are widely used in AI and cloud infrastructure. Compared with the team’s earlier GPUHammer concept, GPUThor’s flip rates are between 4,548 and 23,597 times higher and “approach the bit-flip rates achieved by powerful CPU Rowhammer attacks like Blacksmith,” the researchers write. At those rates, the paper says, finding an exploitable bit flip can take roughly 1.1 minutes versus 21.9 hours with GPUHammer.
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End the scrambleDenial-of-service and root privilege escalation shown
The researchers demonstrated two concrete consequences. First, on an ECC-enabled RTX A6000, GPUThor induced a denial-of-service condition that caused the GPU to reset approximately every two hours, terminating workloads; repeated runs eventually caused the device to mark itself as requiring replacement. Second, and more consequentially, the researchers showed that by corrupting GPU page tables an unprivileged CUDA program could obtain arbitrary memory access and open a root shell on the host. With ECC enabled, GPUThor still produced 387 double-bit errors — which SECDED ECC detects but cannot correct — and two triple-bit errors that ECC repaired incorrectly, producing silent data corruption.
NVIDIA advisory, mitigation guidance, and remaining hardware questions
The researchers reported their findings to NVIDIA on April 29, and on August 21 the company published an advisory with guidance. NVIDIA recommends enabling SYS-ECC and IOMMU/DMA isolation, monitoring GPU error telemetry, and restricting the sharing or execution of untrusted workloads. The company also cautioned that risk varies by DRAM device, memory technology, platform design, in-DRAM defenses, and system configuration, and noted that the researchers observed no bit flips on the tested GDDR6X or HBM2e GPUs using the same attack patterns.
The paper adds nuance on other families: server-class Ampere GPUs such as the A100 remain susceptible in the researchers’ view because they still rely on SECDED-level ECC; some Blackwell GPUs gain time from a RAS Repair resilience feature but are not described as immune; and even HBM3/e and GDDR7 GPUs with on-die ECC “might be vulnerable if multi-bit flips are triggered.” The researchers conclude that complete protection will likely require stronger multi-bit ECC and hardware-level defenses in future GPUs.
What this means for technologists, procurement leaders, and cloud operators
- Technologists and security teams: Expect to monitor ECC error counters and GPU error telemetry closely, restrict untrusted CUDA workloads, and avoid cross-tenant GPU sharing where possible, steps the paper and NVIDIA both recommend.
- Procurement and infrastructure leaders: The vulnerability profile differs by memory technology and platform design; procurement should weigh GPUs’ ECC capabilities and RAS features explicitly with security teams when specifying hardware for shared or multi-tenant environments.
- Cloud operators and tenants: Because the researchers showed privilege escalation from an unprivileged CUDA process, operators that permit tenant-provided GPU code or shared GPUs should consider IOMMU/DMA isolation and stricter workload isolation as immediate mitigations.
The researchers published their paper yesterday and make a stark point about post-compromise realities: even robust prevention scores can hide the risk once an attacker has valid credentials. The University of Toronto team’s metrics — thousands of times better flip rates than prior GPU concepts, short times-to-exploit, demonstrated ECC-detected but uncorrectable errors, and concrete DoS and root escalation results — underline their conclusion that durable defenses will require changes at the hardware ECC and mitigation level as well as operational controls. For teams running Ampere-class workstations or shared GPU fleets, the near-term path is a combination of software isolation, telemetry, and cautious sharing; the longer-term solution, per the paper, is stronger multi-bit ECC and hardware-level redesigns.
