"We demonstrate proof-of-concept attacks on both processors using Spectre-PHT, Spectre-BTB, SpectreRSB, and Spectre-STL, achieving up to 100 percent recall with more than 97 percent precision," the authors write in a paper accepted at the 35th Usenix Security Symposium.
Spectre variants validated on commercial out-of-order RISC-V silicon
Researchers from CISPA Helmholtz Center for Information Security and DistriNet, KU Leuven, report that commercially available out-of-order RISC-V processors are vulnerable to the principal Spectre classes. The paper — titled "Spectre on RISC-V Silicon: Attacks and Defenses on Commercial Out-of-Order Processors" — shows proof-of-concept attacks exploiting Spectre-PHT, Spectre-BTB, Spectre-RSB, and Spectre-STL.
The authors summarize the attack techniques as follows in their paper: Spectre-PHT involves mistraining the Pattern History Table; Spectre-BTB poisons the Branch Target Buffer; Spectre-RSB attacks the Return Stack Buffer; and Spectre-STL (Store To Load) exploits mispredicted store-to-load forwarding. Using those primitives, they report achieving up to 100 percent recall with more than 97 percent precision in their experiments.
SiFive P550 and T-Head Xuantie C910/C920 identified as vulnerable; in-order cores not
The paper states that two families of commercial, out-of-order RISC-V processors — the SiFive P550 and the T-Head Xuantie C910/C920 — are vulnerable to all major Spectre variants tested. By contrast, RISC-V processors that execute instructions in-order, specifically the SiFive U74 and the Xuantie C906 and C908, did not appear to be vulnerable in the authors' experiments.
The authors note that prior academic work had already shown research RISC-V cores (BOOM, RiscyOO, RSD, Proteus, NaxRiscv, and NutShell) can be affected by one or more Spectre variants, but their contribution is to demonstrate the issue on commercial silicon.
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See what we buildProof-of-concept exploit leaks Linux kernel memory at 338 B/s on Xuantie C910
To demonstrate practical impact, the team developed a proof-of-concept Spectre exploit that leaks arbitrary Linux kernel memory on the Xuantie C910. The authors report a measured leakage rate of 338 bytes per second (B/s) for that exploit.
Those experimental results are presented as a concrete signal that the speculative-execution side channels are not only theoretically possible but exploitable on the tested commercial parts.
Mitigations: patches merged, vendor responses, and limits of porting x86/ARM defenses
The authors say they disclosed their findings responsibly in December. According to the paper, three of their patches have been merged into mainline Linux and two additional patches remain under review. SiFive is reported to have addressed P550-specific findings, and T-Head (Alibaba) has committed to publishing ad-hoc speculation barriers for their processors "at some point."
Crucially, the researchers warn that software-based defenses developed for x86 and ARM do not necessarily transfer to RISC-V hardware. They also call out a technical shortfall in RISC-V platforms: a lack of introspection interfaces necessary to observe and reason about microarchitectural features. That absence complicates both detection of vulnerable behavior and the construction of tested mitigations.
What this means for SiFive, T-Head (Alibaba), and mainline Linux maintainers
- SiFive: The paper reports SiFive addressed P550-specific findings. SiFive will likely continue testing and patching P550 variants where the authors' work flagged issues.
- T-Head (Alibaba): T-Head is said to have committed to publishing ad-hoc speculation barriers for their Xuantie C910/C920 processors; the authors' exploit on the C910 underscores urgency for those published barriers to be actionable and tested.
- Mainline Linux maintainers: Three patches from the disclosure have been merged into mainline Linux and two are under review, indicating kernel-level mitigations are being incorporated while vendor-level primitives and hardware transparency lag behind.
The authors summarize the broader technical gap bluntly: "RISC-V inherits the software and threat model of mature architectures without their accumulated hardening." Their prescription is not simply to port individual mitigations from other ISAs, but to "build the architectural primitives, hardware transparency, and ecosystemwide tooling that effective Spectre defense presupposes." They chose not to delay publication because, the authors note, Spectre has been known for eight years.
The paper is authored by Lukas Gerlach (CISPA Helmholtz Center for Information Security), Marton Bognar (DistriNet, KU Leuven), Daniel Weber and Michael Schwarz (CISPA Helmholtz Center for Information Security), and Jo Van Bulck (DistriNet, KU Leuven).
Original story: Spectre rears its ugly head again as researchers show some RISC-V chips are susceptible — The Register
